In many electronic devices, particularly those involved with the transmission and reception of wired or wireless transmissions, there is a need for devices to convert analog signals (e.g., those used to transmit data across a medium) into digital signals (e.g., those used inside the device to identify the data being sent). As a result, the analog-to-digital converter (ADC) is a common element in many electronic circuits.
One kind of circuit that may be used in an ADC is a sigma-delta modulator (SDM). An SDM is a circuit that generates a digital pulse based on an analog signal received at its input. Its output pulses are fixed in width with respect to the amplitude of the received analog waveform. As the amplitude of the input waveform rises, the SDM produces more pulses of a high value; as the amplitude of the input waveform falls, the SDM produces more pulses of a low value. If the amplitude of the input waveform remains neutral, the SDM produces roughly equal numbers of high and low values (i.e., the average should be approximately zero).
An SDM operates on two main principles: oversampling, and noise shaping. Through oversampling, the SDM samples an incoming signal at a sampling frequency that is greater than the signal bandwidth. This spreads the noise power over a bandwidth equal to the sampling frequency. Through noise shaping, the SDM operates as a lowpass filter on the incoming signal, and as a highpass filter on the associated noise. This “shapes” the noise so that most of the energy will be above the signal bandwidth. By employing a digital lowpass filtering stage, the noise can be attenuated out of the signal-plus-noise. And by employing decimation, the sampled signal can be brought to a Nyquist rate for final processing.
In its simplest form an SDM includes an integrator and a comparator with some feedback coming from the comparator to the integrator. The integrator accumulates an input signal over a set time period and the comparator compares that integrated result to a reference to determine whether a digital “1” or a digital “0” has been received during that time period (e.g., a clock cycle). For example, a positive reference voltage might represent a digital “1” value and a negative reference voltage might represent a digital “0” value. In such a circuit, the threshold for the comparator can be set around zero. In operation, if a positive input signal is received, the output of the integrator will tend to accumulate upwards, giving a positive voltage output value that the comparator will determine is a digital “1” value. Likewise, if a negative input signal is received, the output of the integrator will tend to accumulate downwards, giving a negative voltage output value that the comparator will determine is a digital “1” value.
SDMs of higher orders can be formed by adding in additional integrators. Each additional integrator will increase the order by one and will push more noise outside of the passband of the SDM, thus improving the signal-to-noise ratio, among other things.
However, because the SDM uses an integrator, it may overload or become unstable in some circumstances. For example, if the current or voltage input to the integrator is high enough for long enough, the output of the integrator might reach its saturation point. This is particularly true for SDM of higher orders (e.g., third order and higher).
One way to limit integrator saturation or overload is through the use of p-type and n-type diodes to clamp the integrator's output. In this way one diode is connected between the output of an integrator and a positive reference voltage and the other diode is connected between the output of an integrator and a negative reference voltage. The diodes conduct when the integrator output reaches the respective reference voltage, keeping the output of the integrator from passing it. But this may require true dual-isolated wells for both the p-type and n-type diodes, and not all devices have such wells. In addition it can be difficult to generate the required reference voltages.
Another way to limit integrator saturation or overload is to zero the integrator's input when there is a danger of overload or saturation. This can be done by disconnecting the integrator's input and reconnecting it when the danger of overload or saturation is passed. However, this can create transient voltages or currents when the integrator circuitry is disconnected and reconnected, which can be harmful to the circuit's performance.
Still another way to limit integrator saturation or overload is to use power and ground rails to provide natural minimum and maximum output values for the integrator. But with this solution an operational amplifier (op amp) in the integrator may saturate when its output is clamped, debiasing the transistors in the op amp. Rebiasing the op amp may take time, which may be undesirable if speed of operation is important.
In addition, such a solution can reduce linearity. In such circumstances, the bias current for each integrator must be much larger than the maximum output current (e.g., M times larger, where M is an integer greater than 1). In a higher order circuit, when the last integrator saturates, its feedforward element outputs its bias current. This means that the previous integrator's feedforward must output a normal operating current that is larger than the last integrator's feedforward bias current, and so forth down the line, each one being M times larger. In this way bias currents increase exponentially for successively preceding stages, i.e. every stage must have a bias at least M times larger than its subsequent stage. If multiple stages are used, the bias current requirement for the first stage can be extremely high, which can result in very high power consumption.
It is therefore desirable to provide another way of preventing or limiting the saturation or overload of an integrator used in an SDM.